Interface task reset
4096k x 16 buffer detected 
MERC2 - 1_Disk    0.05   01-20-06 15:53
Head Mask 03,01 - Switch to full int.
              Spin Ready
Dwell Cyl - 058D/026A/027F
(P)PATA Reset
Master

T>y
Command Inactive - No VALID Cert Code Detected
T>Interface task reset
4096k x 16 buffer detected 
MERC2 - 1_Disk    0.05   01
Buzz  - -20-06 15:53
Head Mask 03,01 - Switch to full int.
              Spin Ready
Dwell Cyl - 058D/0104/0182
(P)PATA Reset
Master

T>y
Command Inactive - No VALID Cert Code Detected
T>/1
1>r
VALID Cert Disk Code Detected - Revision # .029
1>/0
T>y
                  PhysCyl   GrayCyl 
 1st Sys Cyl      000006CB  00001C59 
 1st 0 Offset Cyl 000006CD  00001C5B 
 1st App Code Cyl 000006DB  00001C69 
 2nd App Code Cyl 000006DD  00001C6B 
 2nd 0 Offset Cyl 000006E1  00001C6F 
 3rd App Code Cyl 000006EF  00001C7D 
 4th App Code Cyl 000006F1  00001C7F 
 1st Adaptive Cyl 000006F3  00001C81 
 1st UsrDfect Cyl 000006F7  00001C85 
 1st Alt Pool Cyl 000006FB  00001C89 
 2nd UsrDfect Cyl 00000705  00001C93 
 1st CertCode Cyl 00000709  00001C97 
 1st IntfCode Cyl 0000070F  00001C9D 
 1st Intf Sys Cyl 00000713  00001CA1 
 1st Cert Log Cyl 00000743  00001CD1 
 1st Decay    Cyl 000007DD  00001D6B 
 1st SPLASH   Cyl 000007F7  00001D85 
 Last System  Cyl 000007F8  00001D86 
T>
